Since the invention of the integrated circuit (IC), the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvement in lithography has resulted in considerable improvement in 2D IC formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
In an attempt to further increase circuit density, three-dimensional (3D) ICs have been investigated. In a typical formation process of a 3D IC, two dies are bonded together and electrical connections are formed between each die and contact pads on a substrate. For example, one attempt involved bonding two dies on top of each other. The stacked dies were then bonded to a carrier substrate and wire bonds electrically coupled contact pads on each die to contact pads on the carrier substrate.
A substrate has been investigated for providing 3D IC packages. In this attempt, a silicon die is attached to a substrate, such as an interposer. The interposer may have through-substrate vias that are used to provide an electrical connection between the integrated circuit die on one side to electrical connections on the other side. Dielectric layers may be formed over the through-substrate vias and metallization layers are formed in the dielectric layers, such as vias formed to provide electrical connections between adjacent metallization layers. In this embodiment, the metallization layers and via sizes increase as the metallization layers extend away from the through-substrate vias.
This configuration, however, may experience open/shorting conditions in the interconnect structure and/or de-lamination/cracking issues. The relative volume of the through-substrate vias and the relative coefficient of thermal expansion (CTE) as compared to the interconnect structure may cause the through-substrate via to “pop” during thermal cycles. The popping of the through-substrate vias may then cause the layers to delaminate or crack, as well as possibly causing a shorting or open condition in the interconnect structure.